1. Field of the Invention
The present invention relates generally to data length detection devices, and in particular, to a data length detection device for detecting the data length of frame data defined by a start flag and a stop flag. The invention has particular applicability to receivers for receiving data in accordance with High Level Data Link Control Procedure (HDLC).
2. Description of the Background Art
High Level Data Link Control Procedure (referred to as "HDLC" hereinafter) is defined by International Organization for Standardization (ISO) as a protocol, and is widely used in various communication fields such as Integrated Service Digital Network (ISDN) and Digital Data Exchange (DDX). HDLC is used, for example, in Link Access Procedure (LAP, LAPB) in packet communication and LAPD for a D channel in ISDN. It is pointed out that the present invention, which will be described below, can be widely utilized in communication system generally in accordance with HDLC.
FIG. 5 is a frame format diagram of HDLC. In HDLC, all the data are transmitted for every frame. One frame is defined by a particular bit pattern "01111110" called a flag. Referring to FIG. 5, data to be transmitted is transmitted in a state interposed between a start flag F1 and a stop flag F2. One frame includes the start flag F1 (1 byte), an address field AF (1 or 2 bytes), a control field CF (1 or 2 bytes), an information field IF (arbitrary), a frame check sequence field FCS (2 bytes), and the stop flag F2 (1 byte). Data in the information field 1F forms data to be originally transmitted, and the data length of the information field, i.e. the byte length can be changed, if necessary.
Generally, if data is transmitted in accordance with HDLC, transmission data satisfying the frame format shown in FIG. 5 is produced in a transmitting apparatus. The produced data is transmitted through a transmission path. The receiving apparatus receives the data transmitted and recognizes the data included in the information field.
FIG. 6 is a block diagram of a receiver in a communication terminal which performs communication control in accordance with the HDLC procedure (hereinafter referred to as HDLC communication terminal). Referring to FIG. 6, the HDLC communication terminal 50 includes a serial data receiver 51 for receiving serial communication data in accordance with HDLC through a transmission path 56, a memory 52 for storing data transmitted thereto, a DMAC part 53 for Direct Memory Access Control (referred to as "DMAC" hereinafter), and a microprocessor 54 for controlling processings in the receiver. A system bus 55 is connected between the serial data receiver 51, the memory 52, the DMAC 53 and the microprocessor 54, so that data transmission in the communication terminal 50 may be performed through the system bus 55.
The operation of the communication terminal shown in FIG. 6 will be described below. One example of the operation, in which data among the received data in the information field is written into the memory 52 will be described. When the serial receiver 51 receives data in accordance with HDLC, a start flag is detected in the serial data receiver 51. In response to the detection of the start flag, a reception start signal RS representing the start of data reception is generated, and the signal RS is applied to the DMAC 53. The DMAC 53 responds to the signal RS to apply to the microprocessor 54 a bus request signal BR for requesting use of the system bus 55. The microprocessor 54 responds to the signal BR, to apply to the DMAC 53 a bus acknowledgement signal BA for acknowledging the use of the system bus 55. Data ID in the information field included in the data received in the serial data receiver 51 is thus transmitted to the memory 52 through the system bus 55 in accordance with the control by the DMAC. The information field data ID is stored in the memory 52. When a stop flag is detected in the serial receiver 51, a reception stop signal RE representing completion of data reception is generated, and the signal RE is applied to the DMAC 53. At the same time, the serial data receiver 51 counts the byte number of the data IB in the information field, and then applies the byte number data IB to the microprocessor 54. The microprocessor 54 recognizes the byte number of the information field data and processes the information field data ID stored in the memory 52.
As can be seen from the above description, the received information field data ID is once stored in the memory 52 in accordance with the control by the DMAC 53, and then read out according to a request from the microprocessor 54.
Although only the data length of the information field in the serial data receiver 51 is detected in the foregoing, the detection of the byte length of data such as address field data or control field data and FCS field data is required, as the case may be. The serial data receiver 51 has such a circuit configuration that detection of the byte length of the data received can be performed in such a case.
One example of the serial data receiver 51 shown in FIG. 6 is shown in FIG. 7. The serial data receiver 51 shown in FIG. 7 represents the background art of the present invention. Referring to FIG. 7, the serial data receiver 51 includes a zero bit deletor 20 for deleting bit "0" inserted by a transmitter (not shown), a flag detector 21 for detecting a start flag and a stop flag, an address field processor 22 for performing a prescribed processing on address field data in received data RD, a control field processor 23 for performing a prescribed processing on control field data included in the received data RD, an FCS field processor 24 for performing a prescribed processing on FCS field data included in the received data RD, and a serial/parallel convertor 25 for converting serial received data RD into parallel data. The flag detector 21 generates a signal FD1 upon detecting a start flag F1 in the received data RD. The flag detector 21 additionally generates a detection signal FD2 upon detecting a stop flag F2 in the received data RD.
The serial data receiver 51 further includes a counter 1 driven by a count timing signal CT generated from the serial/parallel converter 25, a register 8 for holding offset data determined based on data to be counted, an adder/subtracter 7 for performing addition/subtraction of/from the offset data OD and count data CD1 held in the register 8, and a register 2 for holding the resultant data CD2 of the addition/subtraction. A First In First Out (referred to as "FIFO" hereinafter) memory 3 is connected to receive parallel data PD of 8 bit converted by the serial/parallel converter 25. The FIFO memory 3 responds to a count timing signal CT generated from the serial/parallel converter 25 to store the applied data PD.
As mentioned above, the data of the information field IF included in the received data RD has an arbitrary data length. In addition, as the case may be, the byte lengths of data in an address field AF and a control field CF are changed. Accordingly, it is necessary to detect the byte length of data included in the received data RD in the serial data receiver 51 shown in FIG. 7. The serial data receiver 51 shown in FIG. 7 operates as will be described below, in order to detect the byte length of the information field IF included in the received data RD.
After the zero bit deletor 20 deletes an unnecessary bit "0" from the received data RD, the output data is applied to the flag detector 21 and the serial/parallel converter 25. The zero bit deletor 20 further generates an internal operation timing signal CTO, and the signal CTO is supplied to other circuit portions in the serial data receiver 51. The serial/parallel converter 25 responds to the applied data to generate a count timing signal CT, and then applies the same to the counter 1. The flag detector 21 detects a start flag F1 included in the applied data, and applies a start flag detection signal FD1 to the counter 1. The counter 1 responds to the signal FD1, and is driven by the count timing signal CT. In other words, the counter 1 starts counting the byte length of the received data RD.
The adder/subtracter 7 receives the counted data CD1 and the offset data OD. The offset data OD held is set in the register 8 so that data CD2 generated from the adder/subtracter 7 represents only the byte length of the information field IF. In other words, the byte lengths of other fields except for the information field IF are previously known, and the offset data OD to be used on the subtraction of the byte lengths of these data is therefore applied to the adder/subtracter 7. Consequently, the data CD2 representing only the byte length of the information field IF is output from the adder/subtracter 7, and the data CD2 is applied to the register 2. The register 2 responds to a stop flag detection signal FD2 generated from the flag detector 21, and holds the data CD2. The data CD2 held in the register 2 is applied to the microprocessor 54 as the data IB shown in FIG. 6 through the system bus 55. As a result, the byte length of the information field IF in the received data RD is recognized in the microprocessor 54. The byte length of the information field IF may be changed for every frame of the received data RD, the above mentioned operation of detecting byte length is repeated for every frame of each of the received data RD.
In the serial data receiver 51 shown in FIG. 7, the adder/subtracter 7 is provided, and the adder/subtracter 7 should perform subtraction of the offset data OD kept in the register 8 from the data CD1 counted by the counter 1. A certain time period is required for performing the subtraction on these data CD1 and OD, which has been a hindrance to knowing the byte length of the information field in a shorter period of time. Especially, the operation of detecting the byte length is conducted repeatedly as described above, which increased the time delay caused by the adder/subtracter 7. In addition, it is pointed out that the serial data receiver 51 shown in FIG. 7 has a large circuit configuration, and, therefore, the control of which is complicated.